Automatic import of custom designs into a cell-based environment using switch-level analysis and circuit simulation

Abstract

Digital MOS transistor designs are imported into an environment of cell-based tools by division of the design into gate-level components followed by the automatic generation of their logical and timing views. Symbolic switch-level analysis divides the design into channel-connected components and provides estimates of their logical behavior. Electrical simulation verifies or corrects the logical model and yields a timing view.<>