A 200-nanosecond thin film main memory system

Abstract

Several papers have appeared in the last few years which propose a design for large, high-speed memories using planar thin films. Included in this category are memories with greater than 250,000 bits and cycle times of less than 250 nanoseconds. Some authors have set rather high goals of 10 6 bits and 100 nanoseconds cycle time, and, after performing a number of calculations, have concluded that it is indeed possible for such a memory to operate, provided the problems of building it can be solved. Others have presented the results of early, partially implemented models with less ambitious goals, and of course have concluded that a full-sized memory is indeed feasible. These are necessary steps preceding the building of a fully populated, reliable, manufacturable memory. This paper describes the design of such a memory.