Fault Tolerance in VLSI Circuit with Reducing Rollback Cost using FSM

Abstract

In this generation, the revolutionary growth in nanometer technologies brought the drastic change in reduction of device size, increase in complexity, increasing operating speed and decrease in power consumption, which are more sensitive to various kinds of problems. In a combinational logic to protect the faults which are transient are not considered generally as this logic has a common hurdle to stop the faults propagation. In this architecture, there are three cover-up factors used in the process of electrical, logical, and window latch. With these factors, as the industry of processors progress in these days, the chances of generation of transient faults as well as the latches on subsequent element is reduced. Solutions that insulate the whole design are usually very expensive. So that, to implement the rollback, a fixed rollback of K-cycle or a rollback with checkpoint is used. This paper proposes a hardware architecture and the implementations of algorithm, which cut downs the rollback rate in all kind of circuits.