Write stability analysis of 8-T novel SRAM cell for high speed application

Abstract

This paper presents on the stability analysis of the proposed 8-T low power SRAM cell for write operation. Here we propose a novel low power 8-T SRAM cell and compare its stability with conventional 6-T standard models. In the proposed structure we use two voltage sources, one connected with the Bit line and the other connected with the Bit bar line for reducing the voltage swing during the write “0” or write “1” operation. We use 65 nm CMOS technology with 1 volt power supply. Simulation is carried out in Microwind 3.1 by using BSim4 model. We use the approach of write static noise margin, bitline voltage write margin and wordline voltage write margin for analyzing the stability of the proposed SRAM cell. These two extra voltage sources can control the voltage swing at the output node and improve the noise margin during the write operation. The simulation results and the comparison made with that of conventional 6T SRAM justify the efficacy of the superiority of the proposed SRAM structure.