Vertical integration of radiation sensors and readout electronics

Abstract

A semiconductor radiation sensor requires a high-resistivity Si wafer and a high voltage to get a thick radiation sensitive region. Therefore it is difficult to fabricate both sensors and readout electronics in a planer process, and hybrid approach such as mechanical bump bonding have been used. Recently we have developed monolithic radiation detectors based on a 0.2 µm Fully-Depleted Silicon-on-Insulator (FD-SOI) CMOS technology. It has both a thick, high-resistivity sensor layer and a thin LSI circuit layer in a single chip. To shield the electronics part from the sensor region, we have created a buried well region under the buried oxide (BOX) layer of the SOI wafer. Furthermore we are trying to integrate another circuit tier by using a μ-bump technique of 5-µm pitch. This kind of vertical (or 3D) integration is especially important in the pixel detector, since it can increase functionality of a pixel without increasing the pixel size.