An 18-Gb/s $36\times 13 -\mu \mathrm{m}^{2}\ 3.53-\mathrm{mW}\ 2^{7}-1$ PRBS Generator in 40-nm CMOS

Abstract

This paper presents an $18 \mathrm{Gb}/\mathrm{s}\ 2^{7}-1$ pseudo-random binary sequence (PRBS) generator. In the proposed PRBS, two extended truly-single-phase clock (E-TPSC) logic based DFFs are used to shorten the critical path delay and thus improve the data rate. The rest five DFFs are implemented in TSPC logic to save power consumption. Both E-TSPC and TSPC DFF occupy small area. This PRBS is designed in 40-nm CMOS. The post-layout simulation results show 18-Gb/s data rate, $36\times 13-\mu \mathrm{m}^{2}$ core area, 3.S3-mW dc power, and 0.028-pJ/bit FOM.