An Efficient Wirelength Optimization for Booth Multiplier using Silicon Vias

Abstract

In today’s environment, 3D integration is crucial. As technology advances, 3D ICs effectively solve the connectivity issue due to their smaller size, which holds promise for heterogeneous integration. In a 3DIC, the inter-die signal is connected along the vertical axis using TSV. Where HPWL’s (Half Perimeter Wire-Length) role is unsatisfactory, there is no compromise in this case regarding the area and placement of TSVs. The 3D floor planners interpret TSV as points in the pre-processed scenarios, making the placement computation a challenging operation. An effective floor-planner optimises the overall wirelength under a set outline by synchronising the functional modules and the placement of TSV. Even though the wirelength in the most advanced 3D floorplans decreases to 26% from the pre-processed works, there is still a significant runtime overhead. To solve this, a new floor planning algorithm is chosen. Our approach consistently creates superior floorplans with less than 15% shorter wirelength and, on average, less TSVs than the previous state-of-the-art 3D floor-planner with TSV, on which the main focus is placed. Unlike the previous state-of-the-art floor planner, which took hours to complete, our method is atrociously quick enough to layout benchmark with a number of modules. After the routing stage, all PCB effects are removed, including any stray effects that may have been present. The circuit’s progress won’t be hampered in any manner.