Clock-Aware FPGA Placement Contest

Abstract

Modern FPGA device contains complex clocking architecture on top of FPGA logic fabric. To best utilize FPGA clocking architecture, both FPGA designers and EDA tool developers need to understand the clocking architecture and design best methodology/algorithm for various design styles. Clock legalization and clock aware placement become one of the key factors in FPGA design flow. They can greatly influence FPGA design performance and routability. FPGA placement problem can get very difficult with clock legalization constraints. This year's contest is a continuous challenge based on last year's routability driven placement. Contestants need to design best-in-class clock aware placement approach to excel in the contest.