ACMA: Accuracy-configurable multiplier architecture for error-resilient System-on-Chip

Kartikeya Bhardwaj, P. Mane
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引用次数: 33

Abstract

In nanometer regime, optimization of System-on-Chip (SoC) designs w.r.t. speed, power and area is a major concern for VLSI designers today. Imprecise/approximate design obviates the constraints on accuracy, stemming a novel Speed-Power-Accuracy-Area (SPAA) metrics which can pilot to tremendous improvements in speed and/or power with a feeble accord in accuracy. This astonishingly expediency captivated researchers to delve into imprecise/approximate VLSI design evolution. In this paper, we present a new accuracy-configurable multiplier architecture (ACMA) for error-resilient systems. The ACMA uses a technique called Carry-in Prediction for approximate multiplication based on efficient precomputation logic that increases its throughput. The proposed multiplication reduces the latency of an accurate multiplier by almost half by reducing its critical path. The simulation results suggest that SPAA metrics can be administered by exploiting the design for apposite number of iterations. The results for 16-bit multiplication show the mean accuracy of 99.85% to 99.9% in case there is no lower bound on the size of operands and if size of operands are 10-bit or more (numbers > 1000), it results into a mean accuracy of 99.965%.
ACMA:用于抗错误的片上系统的可精确配置乘法器架构
在纳米领域,优化片上系统(SoC)设计(包括速度、功耗和面积)是当今VLSI设计人员关注的主要问题。不精确/近似的设计消除了对精度的限制,产生了一种新的速度-功率-精度-面积(SPAA)指标,可以在精度不高的情况下实现速度和/或功率的巨大改进。这种惊人的权宜之计吸引了研究人员深入研究不精确/近似的VLSI设计演变。在本文中,我们提出了一种新的精度可配置乘法器结构(ACMA)。ACMA使用一种称为随身携带预测的技术来进行基于高效预计算逻辑的近似乘法,从而提高了其吞吐量。所提出的乘法通过减少其关键路径,将精确乘法器的延迟减少了近一半。仿真结果表明,SPAA指标可以通过利用适当次数的迭代设计来管理。16位乘法的结果显示,在操作数大小没有下界的情况下,平均精度为99.85%至99.9%,如果操作数大小为10位或更多(数字> 1000),则平均精度为99.965%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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