ACMA: Accuracy-configurable multiplier architecture for error-resilient System-on-Chip

Abstract

In nanometer regime, optimization of System-on-Chip (SoC) designs w.r.t. speed, power and area is a major concern for VLSI designers today. Imprecise/approximate design obviates the constraints on accuracy, stemming a novel Speed-Power-Accuracy-Area (SPAA) metrics which can pilot to tremendous improvements in speed and/or power with a feeble accord in accuracy. This astonishingly expediency captivated researchers to delve into imprecise/approximate VLSI design evolution. In this paper, we present a new accuracy-configurable multiplier architecture (ACMA) for error-resilient systems. The ACMA uses a technique called Carry-in Prediction for approximate multiplication based on efficient precomputation logic that increases its throughput. The proposed multiplication reduces the latency of an accurate multiplier by almost half by reducing its critical path. The simulation results suggest that SPAA metrics can be administered by exploiting the design for apposite number of iterations. The results for 16-bit multiplication show the mean accuracy of 99.85% to 99.9% in case there is no lower bound on the size of operands and if size of operands are 10-bit or more (numbers > 1000), it results into a mean accuracy of 99.965%.