An equalizer-adaptation logic for a 25-Gb/s wireline receiver in 28-nm CMOS

Abstract

We present an adaptation scheme for a wireline-receiver equalizer composed of a feed-forward equalizer (FFE) and a decision-feedback equalizer (DFE), where the FFE is a cascaded connection of a high-frequency equalizer (HFEQ) and a low-frequency equalizer (LFEQ). The HFEQ is adjusted by using the conventional filter-pattern method. For the LFEQ adjustment, we used a modified filter-pattern method where the pattern matching is performed based on the mark ratio (i.e., the probability of `1'), to enhance the gain of the parameter-adjusting feedback loop. The adaptation is performed in the background, i.e., while data is being received.