Optimization of building blocks for multi-stage 17–44 dB 6.1–9.6 mW 90-nm K-band front-ends

Abstract

In this article, five two-stage ∼6-mW and four three-stage ∼9-mW matched amplifier architectures are proposed to establish optimization procedure and quantify relative merits of cascode (CC), common-gate (CG), and commonsource (CS) building blocks for low-voltage low-power multi-stage front-ends. The circuits are simulated with a 90-nm CMOS technology including modeling of layout parasites. Integrated bias trees and passive port matching networks are incorporated in the K-band designs. In the face of process mismatch, variability in noise and gain figures remains <0.39 dB and <7.1 dB from the design values. The five combinations of building blocks in twostage low-power (6.1–6.6 mW) amplifiers achieve linearity (IIP3) in the range of −5.2∼–13.5 dBm, good reverse isolation (better than −26 dB), 2.89–3.82 dB noise penalties, and 17.2–25.5 dB peak forward gain. In case of threestage front-ends built with CS, CC, and CG blocks (power rating 9.2–9.6 mW), forward gain and optimized noise figures are found as >33 dB and <3.26 dB, respectively. They achieve −2.5∼18.3 dBm IIP3, <−39 dB reverse isolation, and <−17 dB minimum IRL. The results are compared with reported simulated findings on CMOS multistage amplifiers to highlight their relative advantages in terms of power requirement and decibel(gain)-per-watt.