Investigation in burst pulse injection method for fault based cryptanalysis

K. Iokibe, K. Maeshima, H. Kagotani, Y. Nogami, Y. Toyota, Tetsushi Watanabe
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引用次数: 2

Abstract

This paper investigated about introduction of the burst pulse injection method standardized for immunity tests to a cryptanalysis using faulty ciphertexts. We investigated the potential of the burst injection method to induce faulty ciphertexts experimentally. Firstly, the standard burst pulse was injected through the power cable to a cryptographic module implementing the Advanced Encryption Standard (AES) on a field programmable gate array (FPGA). As a result, it was confirmed that the burst pulse injection might cause clock glitches on the module. Secondly, the clock glitch was varied in magnitude and timing by use of two pulse generators and transmitted to the AES circuit to clarify what types of clock glitch induce critical faulty ciphertexts suited for recovering the crypto-key successfully. Results confirmed that the clock glitch had potential to induce faulty ciphertexts when it exceeded the threshold and produced a clock interval shorter than the critical path delay in the target round. The two experimental results suggested that burst pulse injection to cryptographic modules through their power cables is a possible scenario of fault analysis attacks.
基于故障密码分析的突发脉冲注入方法研究
本文研究了针对使用错误密文的密码分析,引入标准化的抗扰性测试的突发脉冲注入方法。我们通过实验研究了突发注入方法诱导错误密文的可能性。首先,将标准突发脉冲通过电源线注入到现场可编程门阵列(FPGA)上实现高级加密标准(AES)的加密模块中。结果证实,脉冲注入可能会导致模块时钟故障。其次,通过使用两个脉冲发生器来改变时钟故障的幅度和时间,并将其传输到AES电路,以澄清哪些类型的时钟故障会导致适合于成功恢复加密密钥的关键故障密文。结果证实,当时钟故障超过阈值并产生比目标轮中的关键路径延迟短的时钟间隔时,时钟故障有可能诱发错误的密文。这两个实验结果表明,通过电源电缆向加密模块注入突发脉冲是故障分析攻击的可能方案。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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