Software pipelining for Jetpipeline architecture

Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN) Pub Date : 1994-12-14 DOI:10.1109/ISPAN.1994.367155

M. Katahira, Takehito Sasaki, Hong Shen, Hiroaki Kobayashi, Tadao Nakamura

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引用次数: 2

Abstract

High performance processors based on pipeline processing play an important role in scientific computation. We have proposed a hybrid pipeline architecture named Jetpipeline in our former work. The concept of Jetpipeline comes from the integration of superscalar, VLIW and vector architectures. Jetpipeline has multiple instruction pipelines, which execute multiple instructions like superscalar architectures. Instructions to be executed simultaneously are statically scheduled by a compiler like VLIW architectures. Therefore, parallelism derivation and instruction scheduling are very important for Jetpipeline. Software pipelining is one of the well-known techniques to achieve high throughput when processing loop programs. In this paper, we propose software pipelining for Jetpipeline. Firstly, the overview of the Jetpipeline architecture is described. Then the banked register configuration of Jetpipeline for reducing hardware complexity and supporting software pipelining is presented. Finally, the effectiveness of software pipelining for Jetpipeline is discussed by simulation.<>

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Jetpipeline架构的软件流水线

基于流水线处理的高性能处理器在科学计算中发挥着重要作用。我们在之前的工作中提出了一个名为Jetpipeline的混合管道架构。Jetpipeline的概念来自于对超标量、VLIW和矢量体系结构的集成。Jetpipeline有多个指令管道，像超标量架构一样执行多个指令。同时执行的指令由像VLIW体系结构这样的编译器静态调度。因此，并行性派生和指令调度对于Jetpipeline来说是非常重要的。软件流水线是处理循环程序时实现高吞吐量的著名技术之一。本文提出了Jetpipeline的软件流水线。首先，概述了Jetpipeline体系结构。然后提出了Jetpipeline的银行寄存器配置，以降低硬件复杂度和支持软件流水线。最后，通过仿真讨论了Jetpipeline软件流水线的有效性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN)

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