A delay locked loop circuit with mixed-mode tuning

Abstract

This paper shows a DLL (delay locked loop) which has a mixed-mode tuning capability. The proposed architecture is based on a dual loop which is controlled by peripheral circuits such as FSM (finite state machine) and two phase detectors whose roles are coarse error detection and fine error detection respectively. The main DLL is composed of eight differential delay buffers and generates eight clocks evenly spaced by 45/spl deg/. The second loop is to produce the retimed clock through coarse timing and fine timing using digital and analog phase control. The circuit has the unlimited phase control range due to the dial loop structure. The circuit operates at 500 MHz under 3.3 V supply according to SPICE simulation on the extracted layout. The circuit will be fabricated in 0.6-/spl mu/m CMOS.