Shien-Yang Wu, Lin Chih-Yung, M. Chiang, J. Liaw, J. Cheng, S. Yang, C. Tsai, P. Chen, T. Miyashita, Chang-Yun Chang, V. Chang, K. Pan, J. Chen, Y. Mor, K. Lai, C. Liang, Chen Hsin-Chi, S. Chang, Chia-Pin Lin, C. Hsieh, R. F. Tsui, C. Yao, C. C. Chen, R. Chen, C. Lee, Hau-Yu Lin, Chih-Sheng Chang, K. W. Chen, M. Tsai, Kuei-Shun Chen, Y. Ku, S. Jang
{"title":"A 7nm CMOS platform technology featuring 4th generation FinFET transistors with a 0.027um2 high density 6-T SRAM cell for mobile SoC applications","authors":"Shien-Yang Wu, Lin Chih-Yung, M. Chiang, J. Liaw, J. Cheng, S. Yang, C. Tsai, P. Chen, T. Miyashita, Chang-Yun Chang, V. Chang, K. Pan, J. Chen, Y. Mor, K. Lai, C. Liang, Chen Hsin-Chi, S. Chang, Chia-Pin Lin, C. Hsieh, R. F. Tsui, C. Yao, C. C. Chen, R. Chen, C. Lee, Hau-Yu Lin, Chih-Sheng Chang, K. W. Chen, M. Tsai, Kuei-Shun Chen, Y. Ku, S. Jang","doi":"10.1109/IEDM.2016.7838333","DOIUrl":null,"url":null,"abstract":"For the first time, a leading edge 7nm CMOS platform technology for mobile SoC applications is presented. This technology provides >3.3X routed gate density and 35%∼40% speed gain or >65% power reduction over our 16nm FinFET technology. A fully functional 256Mb SRAM test-chip with the smallest high density SRAM cell of 0.027um2 is demonstrated down to 0.5V. The 4th generation FinFET transistors are optimized with device mismatch reduction by 25%∼35% and multi-Vt device options to enable low power and high performance design requirements.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"105","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE International Electron Devices Meeting (IEDM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2016.7838333","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 105
Abstract
For the first time, a leading edge 7nm CMOS platform technology for mobile SoC applications is presented. This technology provides >3.3X routed gate density and 35%∼40% speed gain or >65% power reduction over our 16nm FinFET technology. A fully functional 256Mb SRAM test-chip with the smallest high density SRAM cell of 0.027um2 is demonstrated down to 0.5V. The 4th generation FinFET transistors are optimized with device mismatch reduction by 25%∼35% and multi-Vt device options to enable low power and high performance design requirements.
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