Novel polycrystalline gate engineering for high performance sub-100 nm CMOS devices

Abstract

We have developed a design for a polycrystalline (poly-) gate to be used in high performance sub-100 nm CMOS devices. The inversion capacitance (C/sub inv/) in a device with poly-gate was found to obviously decrease as the gate length becomes shorter in the range below 100 nm (C/sub inv/ lowering). The explanation for this C/sub inv/ lowering is as follows: (1) the gate length becoming shorter than the poly-grain size (R/sub G/) and (2) the short dopant-diffusion length from grain boundaries (D/sub H/). Techniques for achieving small values for R/sub G/ and large values for D/sub H/ improved the I/sub D/ figures by +15% for the pFET and by +3% for the nFET that have poly-SiGe gates with L/sub G/=65 nm.