{"title":"Charge Pump with Low Current Mismatch for PLL Applications","authors":"D. Biswas","doi":"10.1109/CONECCT52877.2021.9622662","DOIUrl":null,"url":null,"abstract":"A new error amplifier based charge pump (CP) is proposed. The mismatch current is directed through a high value resistor, and the voltage developed across it is minimized by error amplifier feedback. The loop gain is dependent on the value of the resistor and can be made comparable to conventional error amplifier based CPs. A residual error remains due to finite offset voltages at the branch outputs. This mismatch current is further lowered by dynamically comparing the up and down currents through a clocked comparator and equating the branch output voltages. Simulation results are carried out in 180 nm CMOS technology.","PeriodicalId":164499,"journal":{"name":"2021 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CONECCT52877.2021.9622662","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
A new error amplifier based charge pump (CP) is proposed. The mismatch current is directed through a high value resistor, and the voltage developed across it is minimized by error amplifier feedback. The loop gain is dependent on the value of the resistor and can be made comparable to conventional error amplifier based CPs. A residual error remains due to finite offset voltages at the branch outputs. This mismatch current is further lowered by dynamically comparing the up and down currents through a clocked comparator and equating the branch output voltages. Simulation results are carried out in 180 nm CMOS technology.