Partitioning approach to find an exact solution to the fitting problem in an application-specific EPLD device

Abstract

A new routing-driven partitioning approach for fitting a sequential circuit onto limited-connectivity EPLDs (electrically programmable logic devices) is presented. The fitting problem is stated as a graph monomorphism problem. Global, local, and adjacency routing constraints are used to define the partitioning properties of the graph representing chip resources. This approach very effectively limits the solution space of the graph monomorphism problem in the early stages of the search. The program which uses the proposed algorithm to solve the fitting problem for the CY7C361 device, from Cypress Semiconductor, has been implemented and tested. Solutions to a number of problems unsolved by the previous fitter were found. The experimental results are presented.<>