A 3.5-GHz 6-Bit CMOS Vector-Summing Phase Shifter with Low Phase and Amplitude Errors Using Area-Resizing Technique

Abstract

For a vector-summing phase shifter (VSPS), if the gain of its variable gain amplifiers (VGAs) can be adjusted with fine resolution, low phase and amplitude errors can both be achieved. By adopting area-resizing technique for the design of the VGAs, a 6-bit VSPS is realized using a 0.18-µm CMOS process. Measurement results of the phase shifter show that the RMS phase error is less than 3° and the RMS amplitude error is less than 0.4 dB for more than 2:1 bandwidth.