A scalable 64 channel neurostimulator based on a hybrid architecture of current steering DAC

Abstract

In this work a 130 nm CMOS 64 channel neural stimulator is presented, which is scalable by connecting it in a daisy chain configuration, for applications requiring larger number of stimulation sites, as it is of interest for retinal implants with improved resolution. Each channel is composed of a hybrid architecture current steering 8 bit DAC, enabling the low power consumption and high channel integration on a small chip area. Besides, the DAC allows stimulating with several waveforms in order to save stimulation energy. An on-chip module was implemented to control galvanostatic deposition of PEDOT on the electrodes. A schema is presented to avoid the residual charge due to cross electrode stimulation and process mismatch.