Iterative cache simulation of embedded CPUs with trace stripping

Abstract

Trace-driven cache simulation is a time-consuming yet valuable procedure for evaluating the performance of embedded memory systems. In this paper we present a novel technique, called iterative cache simulation, to produce a variety of performance metrics for several different cache configurations. Compared with previous work in this field, our approach has the following features. First, it supports a wide range of performance metrics, including miss ratio, write-back counts, bus traffic, et al. Second, unlike estimation-based methods, the results produced by our simulator are accurate. Third, our approach is flexible. It can simulate both uniprocessor and multiprocessor caches, with options of higher level caches, sub-block replacement and prefetching. Last, it is fast. Our simulation results show that it has similar runtime as the fastest one-pass cache simulator.