Induced Passivation Defect Study

Abstract

An n-channel FET memory array chip whose quartz passivation layer is purposely disrupted in specific-nonrandom locations is used to study the propensity of these induced defects to fail due to localized inversion of the silicon surface stemming from positive ions contained within the defect which are residual from processing. Two distinct sizes of induced defects are considered; three and seven micron diamters; 800 of the larger size and 100 of the smaller. Vertical structures range from shallow indentations to holes completely-through the passivation layer thus exposing the underlying silicon. Positive ionic contamination is introduced into the defects via an overcoat of photoresist whose positive ionic species and levels are known. Accelerated temperature and voltage life stresses are performed. Temperatures employed are 85 and 150°C, while voltage levels (and E field) across the defect are nominal and twice nominal. Data obtained from these temperature/voltage accelerated stresses is presented which shows time-to-fail is related to the ionic (mostly sodium) levels contained within the defects. Voltage acceleration was found to be a nonlinear function while temperature follows the standard Arrhenius model with an activation energy of 1.1 eV. Hole size was found to be at best a second order effect on time-to-fail. High temperature no bias bake-out at 150°C for 48 hours was performed. Percent inversion is seen to decrease by approximately an order of magnitude in all cases.