Low-Power VLSI Architecture for Neural Data Compression Using Vocabulary-based Approach

Abstract

Modern-day bio-implantable chips for neural prostheses cannot monitor a large number of electrodes at the same time since they suffer from excessively high data rates. Hence, it is imperative to design area and power-efficient digital circuits for appropriate conditioning of the recorded neural signal in order to remain within the bandwidth constraint. Previously, we have proposed an algorithm for neural data compression, which incorporates the concept of creating and maintaining a dynamic vocabulary of neural spike waveforms represented as wavelet transform coefficients. In this paper, we propose an appropriate architecture for low-power and area-efficient VLSI implementation of the scheme. Based on simulation results, the hardware consumes 3.55 muW and 0.36 mW power using 0.18 mum CMOS technology for 1-channel and 100-channel neural recording applications, respectively.