Experimental investigation, simulation and analyses of avalanche effects on power MOSFETs

Abstract

Circuit simulation was performed using a new power MOSFET model in order to investigate avalanche effects in such devices. Experimental measurements were also conducted and correlated with the simulation. It is shown that the avalanche effect taking place on the edge of the p-well can lead to destruction of the device and should be avoided, whereas the avalanche effect taking place at the bottom of the p-well is less critical. This effect can be alleviated by the circuit design, e.g. a Schottky diode at the input or a sufficient output current. However, the circuit designer must take into account that this avalanche mode causes additional losses, and a careful circuit design should avoid the avalanche effect.<>