P. K. Chakravathi, K. V. Kumar, P. Devi Pradeep, D. Suresh
{"title":"FPGA based architecture for realtime edge detection","authors":"P. K. Chakravathi, K. V. Kumar, P. Devi Pradeep, D. Suresh","doi":"10.1109/GCCT.2015.7342615","DOIUrl":null,"url":null,"abstract":"Edge Detection is one of the basic characteristics of the image. It is an important basis for the field of image analysis such as image segmentation, target area identification, extraction and other regional forms. The edge detection operators such as canny, sobel, prewitt operators detects the wide range of edges in image. These operators apply the convolution operation at each pixel to have gradient image. FPGA (Field programmable gate array) is fine grained reconfigurable architecture that can virtually perform any processing operation at a hardware level and satisfying real-time requirements for image processing. In FPGA hardware resources there are rich internal multipliers. The design process can directly call these resources to operate, so it is easy to implement complex convolution. FPGA based architecture for real time edge detection presents a new flexible parameterizable architecture which reduces latency and memory requirements. This architecture contains neighborhood extractors and threshold operators that can be parameterized at runtime. The algorithm simplifications reduces mathematical complexity, memory requirements, and latency without losing reliability. This architecture has clear advantage in terms of power consumption and maintain a reliable performance with noisy images.","PeriodicalId":378174,"journal":{"name":"2015 Global Conference on Communication Technologies (GCCT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 Global Conference on Communication Technologies (GCCT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GCCT.2015.7342615","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
Edge Detection is one of the basic characteristics of the image. It is an important basis for the field of image analysis such as image segmentation, target area identification, extraction and other regional forms. The edge detection operators such as canny, sobel, prewitt operators detects the wide range of edges in image. These operators apply the convolution operation at each pixel to have gradient image. FPGA (Field programmable gate array) is fine grained reconfigurable architecture that can virtually perform any processing operation at a hardware level and satisfying real-time requirements for image processing. In FPGA hardware resources there are rich internal multipliers. The design process can directly call these resources to operate, so it is easy to implement complex convolution. FPGA based architecture for real time edge detection presents a new flexible parameterizable architecture which reduces latency and memory requirements. This architecture contains neighborhood extractors and threshold operators that can be parameterized at runtime. The algorithm simplifications reduces mathematical complexity, memory requirements, and latency without losing reliability. This architecture has clear advantage in terms of power consumption and maintain a reliable performance with noisy images.