Parallel 3-Pixel Labeling Method and its Hardware Architecture Design

Abstract

In this paper, we present a parallel connected component labeling method and its VLSI architecture design. The proposed method can assign labels to three pixels simultaneously for the raster scan input and then generate three label equivalences rapidly. We also present 3 arrays to process all label mergence. Based on the proposed method, we develop the hardware design for real-time application. The parallel architecture efficiently reduces total execution cycle significantly. From the experimental results, our 3-pixel labeling design can save 66% and 33% of the execution cycle comparing with the designs by 1-pixel labeling and 2-pixel labeling approaches, respectively.