Cluster-based topologies for 3D stacked architectures

Abstract

As Three Dimensional Integrated Circuits (3D ICs) have been emerging as a viable candidate to achieve better performance and package, combining the benefits of 3D IC and Network-on-Chip (NoC) schemes provides a significant performance gain for 3D architectures. Through-Silicon-Via (TSV), employed for inter-layer connectivity (vertical channel)in 3D ICs, reduces wafer utilization and yield which impact design of 3D architectures using a large number of TSVs. In this paper, we propose two novel stacked topologies for 3D architectures to reduce the area overhead of TSVs and power dissipation on each layer with minimal performance penalty. The presented schemes benefit of clustering the mesh topology in order to mitigate TSV footprint on each stacked layer.