Design and simulation of CMOS LNA for down converting sigma-detla ADC for reconfigurable RF receiver

B. Tasadduq
{"title":"Design and simulation of CMOS LNA for down converting sigma-detla ADC for reconfigurable RF receiver","authors":"B. Tasadduq","doi":"10.1109/ICSENGT.2011.5993413","DOIUrl":null,"url":null,"abstract":"In this paper, we propose simulation results of a wideband Low noise amplifier(LNA) for down converting sigma-delta A/D converter for reconfigurable RF receiver architecture [1]. The proposed LNA is designed for frequency range of 1.7GHz to 10GHz providing a gain of 7.5–9.766 dB, noise figure of 1.454–5.166dB, input matching of −5.77 to −23.8 dB, IIP3 and P1dB of 6.7dBm and 17.2dBm and stability over the entire frequency spectrum. The power dissipation is 7.404mW from 1.5V supply. The simulations are performed on Cadence RF specter.","PeriodicalId":346890,"journal":{"name":"2011 IEEE International Conference on System Engineering and Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE International Conference on System Engineering and Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSENGT.2011.5993413","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

Abstract

In this paper, we propose simulation results of a wideband Low noise amplifier(LNA) for down converting sigma-delta A/D converter for reconfigurable RF receiver architecture [1]. The proposed LNA is designed for frequency range of 1.7GHz to 10GHz providing a gain of 7.5–9.766 dB, noise figure of 1.454–5.166dB, input matching of −5.77 to −23.8 dB, IIP3 and P1dB of 6.7dBm and 17.2dBm and stability over the entire frequency spectrum. The power dissipation is 7.404mW from 1.5V supply. The simulations are performed on Cadence RF specter.
可重构射频接收机下变频σ - δ ADC CMOS LNA的设计与仿真
在本文中,我们提出了一个宽带低噪声放大器(LNA)的下转换σ - δ a /D转换器的可重构射频接收机结构[1]的仿真结果。该LNA的设计频率范围为1.7GHz至10GHz,增益为7.5 ~ 9.766 dB,噪声系数为1.454 ~ 5.166dB,输入匹配度为- 5.77 ~ - 23.8 dB, IIP3和P1dB分别为6.7dBm和17.2dBm,在整个频谱范围内保持稳定。1.5V电源的功耗为7.404mW。在Cadence RF幽灵上进行了仿真。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信