26.6 A 5GS/S 150mW 10b SHA-less pipelined/SAR hybrid ADC in 28nm CMOS

Abstract

The recent emergence of direct sampling in residential broadband satellite and cable receivers has spurred the need for low-power, high-speed (~5GS/s), mid-resolution (~10b) A/D converters. Recently, time-interleaved (TI) SARs have been a popular choice for low-power, medium-speed, mid-resolution ADCs [1-3]. As the conversion rate and resolution requirements increase, TI-SARs become less attractive in terms of power efficiency and complexity compared to TI-pipelined ADCs [4], where the critical SNR, THD, and TI matching are only required in the MDACs resolving the MSBs. In this paper we report a hybrid of TI-pipelined MDAC and TI-SAR, in which the former resolves the 2 MSB bits and the latter resolves the 8 lower bits. This hybrid architecture combines the advantages from each ADC type to achieve better power at 5GS/s. The front-end is implemented by time-interleaving two 2.5b MDAC slices, easing the timing-matching requirement and complexity. The MDAC stage also eases the timing-matching requirement among the TI-SARs by presenting an amplified-and-held signal to each SAR input. This allows taking advantage of a low-resolution SAR's simplicity and low power, for the last 8b. This work also proposes a SHA-less front-end to further minimize the ADC power. Two simple calibration techniques are introduced on-chip to enable the topology: (a) an over-range calibration (ORcal) loop to correct the sampling-time error between MDAC and sub-ADC in the SHA-less front-end, and (b) SAR reference calibration to align the SAR's full-scale to the MDAC's. Figure 26.6.1 shows the timing and functional block diagram of the 5GS/s hybrid SHA-less ADC. The RF buffer directly drives two TI-slices, each comprising a 2.5GS/S MDAC stage to resolve the 2.5 MSB bits, followed by 4-way interleaved 625MS/S SARs to resolve the lower 8b, for a combined 10b resolution (1b overlap), at 5GS/s.