A novel VHDL implementation of UART with single error correction and double error detection capability

Abstract

In an industrial working environment employing multiprocessor communication using UART, noise is likely to affect the data and data may be received with errors. This kind of error occurrence may affect the working of the system resulting in an improper control. Several existing UART designs are incorporating error detection logic. This kind of logic, if detects errors, requires retransmission of corresponding data frames which take additional time for automatic repeat request (ARQ) and retransmission of data. Linear block codes like hamming code have forward error correction (FEC) as well as error detection capability. This paper presents a novel VLSI implementation of UART designed to include (8,4) extended hamming code called SEC-DED code that can correct upto one error and detect upto two errors. This improves the noise immunity of the system optimizing the error free reception of data. The whole design is implemented in Xilinx ISE 12.3 simulator targeted to Xilinx Spartan 6 FPGA.