Analytical Exploration of Stepped Asymmetric Workfunction Modulated Trenched Stack Gate Silicon-on-Insulator MOSFET for Advancement of SCEs

2021 International Conference in Advances in Power, Signal, and Information Technology (APSIT) Pub Date : 2021-10-08 DOI:10.1109/APSIT52773.2021.9641475

Sikha Mishra, Soumva S. Mohanty

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Abstract

A thoughtful analysis of an innovative stepped asymmetric stack gate structure with graded workfunction has been assembled for rectangular trenched gate (SAS-GWRTG) silicon on insulator (SOI) MOSFET on TCAD device simulator. A compact model for the proposed structure has been formulated by solving the Poisson's equation. This structure takes advantage of the recessed channel to enhance the short channel effects (SCEs) and stepped stack gate at the drain side to improve the hot carrier effect. Further with graded work-function at the source side gate provides an enhanced device analog performance. The influence of negative junction depth (NJD) is explored on the sub-threshold parameters to achieve an optimized device performance. Investigation reveals the enhanced performance manifested by the proposed structure with better switching behaviour, high immunity to SCEs, and increased carrier transportation efficiency. So, this meaningful research is relatively beneficial for nano-scaled short channel devices.

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阶梯式非对称工作函数调制沟槽堆叠栅绝缘子上硅MOSFET的分析探索

在TCAD器件模拟器上对矩形沟槽栅极(SAS-GWRTG) MOSFET的一种具有梯度工作函数的创新阶梯非对称堆叠栅极结构进行了深入的分析。通过求解泊松方程，建立了该结构的紧凑模型。该结构利用了凹槽通道增强短通道效应(ses)和漏侧阶梯式堆叠栅极来改善热载子效应。此外，在源侧栅极的分级工作功能提供了增强的设备模拟性能。探讨了负结深度(NJD)对亚阈值参数的影响，以优化器件性能。研究表明，该结构具有更好的开关性能，对sce的免疫能力强，载流子传输效率高。因此，这一有意义的研究对纳米尺度的短通道器件具有相对有益的意义。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2021 International Conference in Advances in Power, Signal, and Information Technology (APSIT)

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