An effective routing methodology for Gb/s LSI using deep submicron CMOS/SIMOX technology

Abstract

This paper presents the routing methodology and CAD tools used in designing Gb/s LSIs with deep submicron technology. A routing method for controlling wire width and spacing is adopted for each net group classified by wire length and the permitted delay constraints. A high-performance router and a high-precision delay analyzer adapted to the methodology have been developed. The methodology has been applied in the design of an ATM-switch LSI using 0.25 /spl mu/m CMOS/SIMOX technology. The LSI has a throughput of 40 Gb/s (2.5 Gbps/pin) and an internal clock frequency of 312 MHz.