A methodology for worst-case design of BiCMOS integrated circuits

Abstract

A corners methodology for BiCMOS is derived using CMOS corners as the basis. Five corners for CMOS are proposed. Coupled to the four axis corners are two bipolar corners per CMOS corner. This implies that for BiCMOS there are a total of nine possible transistor corners that are superimposed on temperature, voltage, and resistor variation. Physical correlation between MOS and bipolar parameters is taken into account by using numerical and analytical techniques. Both lithographic and diffusion/film variations are accounted for in the methodology. Using the described approach, nonphysical corners are eliminated and the total number of possibilities is restricted to those of practical interest. Resulting corners circuit simulations clearly show the advantage of using physically based worst-case process files. Also demonstrated is the robustness of the basic BiCMOS gate with respect to worst-case process files and temperature.<>