Simulation in 3D integration and TSV

Abstract

The development of 3D-silicon integrated circuits is an increasing demand especially regarding to advanced 3D-packages and high performance applications, with the intend to miniaturize and to reduce costs. Through-silicon-vias (TSV), interconnects and landing pads have a strong mismatch in proportions. Due to high temperature as well as high applied currents, the reliability of the systems and components is affected by thermal and thermal-electrical loads. The induced stress leads to degradation effects like electro- and thermomigration (EM, TM). Mismatch in coefficient of thermal expansion (CTE) are causing mechanical induced stress during the manufacturing process. This can lead to failure mechanisms like delamination and cracking around the TSV or in the ICs.