{"title":"A Simulation-Based Method for Fault Tolerance Evaluation","authors":"C. Scheper, R. Baker","doi":"10.1109/SSST.1992.712188","DOIUrl":null,"url":null,"abstract":"Digital computing systems are used in many applications to perform functions whose correct execution is critical to the application, to the mission the application is a part of, or to human life and safety. This has led to an emphasis on the dependability of computing systems, i.e., whether or not justifiable reliance can be placed upon the service delivered by the system. There can be many factors defining dependability for a particular system, including performance, functionality, fidelity, reliability, maintainability, availability testability, fault tolerance, safety, security, and life-cycle cost. These factors interact with each other in ways that can be mutually diminishing and that can result in an undependable system. Therefore, a rigorous dependable system design validation and verification methodology is required. This paper addresses one of the necessary components of such a methodology for highly reliable systems: fault tolerance evaluation. We define fault tolerance evaluation to be those activities that assure that appropriate fault tolerance mechanisms are designed and implemented to provide the required level of system reliability, and propose an approach for using directed graph simulation models, behavioral simulation models, and semi-Markov analytic models during the early- to mid-stages of design for fault tolerance evaluation.","PeriodicalId":359363,"journal":{"name":"The 24th Southeastern Symposium on and The 3rd Annual Symposium on Communications, Signal Processing Expert Systems, and ASIC VLSI Design System Theory","volume":"52 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"The 24th Southeastern Symposium on and The 3rd Annual Symposium on Communications, Signal Processing Expert Systems, and ASIC VLSI Design System Theory","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SSST.1992.712188","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Digital computing systems are used in many applications to perform functions whose correct execution is critical to the application, to the mission the application is a part of, or to human life and safety. This has led to an emphasis on the dependability of computing systems, i.e., whether or not justifiable reliance can be placed upon the service delivered by the system. There can be many factors defining dependability for a particular system, including performance, functionality, fidelity, reliability, maintainability, availability testability, fault tolerance, safety, security, and life-cycle cost. These factors interact with each other in ways that can be mutually diminishing and that can result in an undependable system. Therefore, a rigorous dependable system design validation and verification methodology is required. This paper addresses one of the necessary components of such a methodology for highly reliable systems: fault tolerance evaluation. We define fault tolerance evaluation to be those activities that assure that appropriate fault tolerance mechanisms are designed and implemented to provide the required level of system reliability, and propose an approach for using directed graph simulation models, behavioral simulation models, and semi-Markov analytic models during the early- to mid-stages of design for fault tolerance evaluation.