High-performance energy-efficient memory circuit technologies for sub-45nm technologies

Abstract

This tutorial discusses challenges and design solutions for high-performance energy efficient memory/register file circuit design. Technology scaling trends for leakage and process variation for sub-45nm technologies are analyzed, with special emphasis on their impact on wide fan in OR gates found in high performance register file. Novel high-speed and leakage/process tolerant circuits are reviewed. Leakage/process sensors which enable these processes compensating techniques are presented.