K. Miyahara, D. Kanemoto, R. Pokharel, K. Yoshida, H. Kanaya
{"title":"Development of dual band digitally controlled oscillator using Fibonacci sequence in 0.18 um CMOS process","authors":"K. Miyahara, D. Kanemoto, R. Pokharel, K. Yoshida, H. Kanaya","doi":"10.1109/TENCON.2013.6718451","DOIUrl":null,"url":null,"abstract":"This paper presents a digitally controlled oscillator (DCO) in inductor-capacitor (LC) topology with dual -band and fine frequency tuning steps. Using special Fibonacci sequence method and additional capacitor in the capacitor bank, this DCO operates two differential frequency bands and achieves finer tuning range than that of a conventional binary sequence DCO. The proposed circuit is implemented in 0.18 um CMOS technology and tested. It has a high-band frequency of 4.01-4.54 GHz and low-band frequency of 3.41-3.74 GHz. The measured phase noise is -119.3 and -104.5 (dBc/Hz at 1MHz offset) at carrier frequency at 4.54 GHz and 3.41 GHz.","PeriodicalId":425023,"journal":{"name":"2013 IEEE International Conference of IEEE Region 10 (TENCON 2013)","volume":"86 3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE International Conference of IEEE Region 10 (TENCON 2013)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TENCON.2013.6718451","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper presents a digitally controlled oscillator (DCO) in inductor-capacitor (LC) topology with dual -band and fine frequency tuning steps. Using special Fibonacci sequence method and additional capacitor in the capacitor bank, this DCO operates two differential frequency bands and achieves finer tuning range than that of a conventional binary sequence DCO. The proposed circuit is implemented in 0.18 um CMOS technology and tested. It has a high-band frequency of 4.01-4.54 GHz and low-band frequency of 3.41-3.74 GHz. The measured phase noise is -119.3 and -104.5 (dBc/Hz at 1MHz offset) at carrier frequency at 4.54 GHz and 3.41 GHz.