Analysis of Glitch Reconvergence in Combinational Logic SER Estimation

Abstract

Much effort has been made to estimate SER (Soft error rate) in combinational logic. However, little of them involve glitch reconvergence. In this paper, we discuss how to estimate SER in combinational logic when considering reconvergence. We present Boolean difference expressions for the sensitization condition of six reconvergence categories so that symbolic technique can be used to compute logical masking of reconvergence. We develop an equivalent glitch method so that STA (Static Timing Analysis) like pre- characterization method can be applied to compute electrical masking of reconvergence. Furthermore, latching window masking of reconvergence is discussed. Experiment results of ISCAS'85 benchmark circuit show that considering of reconvergence will cause overall 13.9% SER reduction. The time and memory cost of our method is moderate. And the average error of our method is 3.3% relative to SPICE.