Sensitivity analysis of a radiation immune CMOS logic family under defect conditions

Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium Pub Date : 1993-04-06 DOI:10.1109/VTEST.1993.313378

Erik H. Ingermann, J. Frenzel

引用次数: 0

Abstract

Simulation of resistive shorts is performed on a recently developed single event upset immune logic family. Critical resistances and resultant transition delay times are compared with those of traditional CMOS logic. Behavior of the logic under these simulated defects is discussed.<>

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缺陷条件下辐射免疫CMOS逻辑族的灵敏度分析

对新近开发的单事件干扰免疫逻辑家族进行了电阻短路仿真。将临界电阻和由此产生的过渡延迟时间与传统CMOS逻辑进行了比较。讨论了在这些模拟缺陷下的逻辑行为。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium

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