NetCracker: A Peek into the Routing Architecture of Xilinx 7-Series FPGAs

Morten B. Petersen, Stefan Nikolic, Mirjana Stojilović
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引用次数: 10

Abstract

Novel applications have triggered significant changes at the system level of FPGA architecture design, such as the introduction of embedded VLIW processor arrays and hardened NoCs. However, the routing architecture of the soft logic fabric has largely remained unchanged in recent years. Since hunger for acceleration of ever more varied tasks with various power budgets---as well as complications related to technology scaling---is likely to remain significant, it is foreseeable that the routing architecture too will have to evolve. In this work, we do not try to suggest how routing architectures of tomorrow should look like. Instead, we analyze an existing architecture from a popular commercial FPGA family, discussing the possible origins of various design decisions and pointing out aspects that may merit future research. Moreover, we present an open-source tool that greatly eases such analyses, relying only on data readily available from the vendor CAD tools. Our hope is that this work will help the academic research community in catching up with the current developments in industry and accelerate its contributions to FPGA architectures of the future.
NetCracker:窥视Xilinx 7系列fpga的路由架构
新的应用已经引发了FPGA架构设计系统级的重大变化,例如嵌入式VLIW处理器阵列和强化noc的引入。然而,软逻辑结构的路由体系结构近年来基本保持不变。由于对各种功率预算的各种任务的加速需求以及与技术扩展相关的复杂性可能仍然很重要,因此可以预见,路由架构也将不得不发展。在这项工作中,我们并没有试图建议未来的路由架构应该是什么样子。相反,我们分析了一个流行的商用FPGA家族的现有架构,讨论了各种设计决策的可能起源,并指出了可能值得未来研究的方面。此外,我们提出了一个开源工具,它极大地简化了这种分析,仅依赖于从供应商CAD工具中随时可用的数据。我们希望这项工作将帮助学术研究界赶上当前的工业发展,并加速其对未来FPGA架构的贡献。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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