Two Strained-Si Layers in Channel Region of HOI MOSFET

Abstract

A heterostructure design with two strained silicon (s-Si) layers on both side of the middle layer strained silicon germanium (s-SiGe) layer, forming a tri-layered channel heterostructure-on-insulator (HOI) metal oxide semiconductor field effect transistor (MOSFET) have been developed. Quantum carrier confinement ensued within both the ultrathin s-Si layers, which instigates mobility enhancement, and hence counter balances the threshold voltage (Vth) roll-off due to the strained layers in the channel region. A comparison of the conventional single s-Si on relaxed SiGe channel HOI MOSFET with double s-Si channel HOI MOSFET have been perceived leading to eloquent drain current enhancement of $\sim49\%$ for channel length, Lg=100nm due to the captivity of carriers with trivial reduction in the threshold voltage caused on the additional bottom s-Si layer. An in depth analysis of the device in the nanoscale regime for Device-B (Lg=50nm) and Device-C (Lg=40nm) have exemplified superior device characteristic without scaling down the overall device geometry, leading to prominence of velocity overshoot condition under low-scattering effect, augmenting mobility and drift velocity, while approaching to the quasi ballistic carrier transport mechanism in the channel, therefore remarkably improving drive current of the nano-MOSFET.