A 1.2V 10b 20MSample/s non-binary successive approximation ADC in 0.13/spl mu/m CMOS

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI:10.1109/ISSCC.2002.992993

Franz Kuttner

引用次数: 99

Abstract

A successive-approximation ADC with non-binary code achieves 55dB SNR at sampling frequencies up to 20MHz. The converter, with on-chip driver for analog input and reference input, measures 0.08mm/sup 2/ in a standard 0.13/spl mu/m CMOS process and consumes 12mW from a single 1.2V supply.

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在0.13/spl mu/m CMOS中的1.2V 10b 20MSample/s非二进制逐次逼近ADC

具有非二进制码的连续逼近ADC在高达20MHz的采样频率下实现55dB的信噪比。该转换器具有用于模拟输入和参考输入的片上驱动器，在标准的0.13/spl mu/m CMOS工艺中测量0.08mm/sup 2/，单个1.2V电源消耗12mW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)

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