New access resistance extraction methodology for 14nm FD-SOI technology

Abstract

In this work, an improved methodology of access resistance extraction is proposed and applied on dedicated Kelvin test structures from a FD-SOI 14 nm technology. The use of this new approach and these test structures allow to confirm that the parasitic resistance of advanced MOSFET is highly dependent of the gate voltage. This explains the impossibility to decorrelate intrinsic and access components using Y function method for very small gate length transistors. A simple phenomenological model for MOSFETs access resistance is proposed and validated at the drain current level.