VLSI implementation of a reduced memory bandwidth real-time EZW video coder

Abstract

The architecture of a real-time wavelet video coder is described, with the main emphasis put on the memory bandwidth reduction and efficient VLSI implementation. The proposed architecture adopts a modified 2D subband decomposition scheme, along with a parallelized pipelined embedded zerotree wavelet coder architecture. The video encoder is integrated in a 0.35 /spl mu/m 3LM chip by using 341000 transistors on a 4.93/spl times/4.93 mm/sup 2/ die, which can process 720/spl times/480 30 fps pictures in real-time.