Optimizing the wafer dicing process

Abstract

Wafer dicing is one of the critical elements of the IC assembly process where improvements can make a major contribution to yield. Chipping (damage along the cut line inherent to the wafer dicing operation) has been identified by semiconductor manufacturers as a relevant area for improvement. A study of process factors that affect the magnitude of the chipping phenomenon is described. The goal is to explore the limits of the current equipment. Cursory experiments are conducted to zero-in on significant factors. During this phase, several factors that were considered major causes for chipping, are found to have no significant effect. A set of designed experiments is run. It identifies chipping sensitivity to process parameters and points at an operating window that improves cut quality. Field tests in production environment confirm the experimental results.<>