A State-Configurable IIC Bus Design

Abstract

This paper presents a design of IIC bus with configurable state and readable flexibility. Based on the proposed design, the working state of IIC can be read at all times, and simultaneously can be configured through APB bus. The implementation of finite state machine design is adopted, in which a small state machine is embedded into a large state machine, and state information is updated in IIC registers in real time. Through RTL simulation and FPGA verification, reliable data transmission in slave devices with IIC bus interface is realized. This proposed design has good flexibility, and suitable for chip measurement and system debugging, and has been successfully applied in engineering practice.