RAMS: a VHDL-AMS code refactoring tool supporting high level analog synthesis

Abstract

In this paper, a code refactoring methodology for the high-level analog synthesis is presented. It restructures, refines, and simplifies an analog behavioral model written in VHDL-AMS. Through code refactoring one improves the comprehensibility, expandability and reusability of the behavioral model and brings the model to a necessary preliminary stage for the actual circuit synthesis. This approach supports the top-down hierarchical design flow for analog and mixed-signal application.