A novel time register with process and temperature calibration

Orfeas Panetas-Felouris, S. Vlassis
{"title":"A novel time register with process and temperature calibration","authors":"Orfeas Panetas-Felouris, S. Vlassis","doi":"10.1109/MOCAST52088.2021.9493414","DOIUrl":null,"url":null,"abstract":"This paper presents a novel time register circuit suitable for time-based or time-domain signal processing. The proposed circuit is based on the capacitor discharging method and is compensated against technology process and chip temperature variations using a novel calibration loop based on master-slave approach. The loop contains a high-speed comparator based on simple current-starved inverter logic along with a triple-point threshold voltage stabilization loop. The circuit is designed using 28nm Samsung FD-SOI process under 1V supply voltage with 10MHz operating frequency. Simulation results present an almost constant capacitor voltage discharging slope of the time register over worst case process corners and temperature between 0°C and 100°C while consuming only 10μA.","PeriodicalId":146990,"journal":{"name":"2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MOCAST52088.2021.9493414","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5

Abstract

This paper presents a novel time register circuit suitable for time-based or time-domain signal processing. The proposed circuit is based on the capacitor discharging method and is compensated against technology process and chip temperature variations using a novel calibration loop based on master-slave approach. The loop contains a high-speed comparator based on simple current-starved inverter logic along with a triple-point threshold voltage stabilization loop. The circuit is designed using 28nm Samsung FD-SOI process under 1V supply voltage with 10MHz operating frequency. Simulation results present an almost constant capacitor voltage discharging slope of the time register over worst case process corners and temperature between 0°C and 100°C while consuming only 10μA.
一种具有过程和温度校准的新型时间寄存器
本文提出了一种适用于基于时间或时域信号处理的新型时间寄存器电路。该电路基于电容放电方法,并采用一种基于主从方法的新型校准回路对工艺过程和芯片温度变化进行补偿。该回路包含一个基于简单缺流逆变器逻辑的高速比较器以及一个三点阈值电压稳定回路。电路采用28nm三星FD-SOI工艺,在1V电源电压和10MHz工作频率下设计。仿真结果表明,在最坏情况下,在0°C和100°C之间的温度范围内,时间寄存器的电容电压放电斜率几乎恒定,而功耗仅为10μA。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信