{"title":"A novel low-power high-speed programmable dual modulus divider for PLL-based frequency synthesizer","authors":"M. Sulaiman, N. Khan","doi":"10.1109/SMELEC.2002.1217779","DOIUrl":null,"url":null,"abstract":"A low-power high-speed programmable dual modulus divider architecture is presented. The circuit's three building blocks: prescaler, 2- and 5-bit programmable dividers; were designed using high-performance single-phase clocking latch-up circuits rather than the conventional latch-up circuits widely used in digital systems. The dividers operate based on the modulus control and parallel loading concepts, capable of operating within the division ratio of 32-127. The programmable dual-modulus divider with 2.4 GHz maximum operating frequency was designed using the 0.18-/spl mu/m CMOS technology. Post parasitics-extracted layout results verify that the total power dissipation was 2.3 mW (at 2.4 GHz, 1.8 V).","PeriodicalId":211819,"journal":{"name":"ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2002-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SMELEC.2002.1217779","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
A low-power high-speed programmable dual modulus divider architecture is presented. The circuit's three building blocks: prescaler, 2- and 5-bit programmable dividers; were designed using high-performance single-phase clocking latch-up circuits rather than the conventional latch-up circuits widely used in digital systems. The dividers operate based on the modulus control and parallel loading concepts, capable of operating within the division ratio of 32-127. The programmable dual-modulus divider with 2.4 GHz maximum operating frequency was designed using the 0.18-/spl mu/m CMOS technology. Post parasitics-extracted layout results verify that the total power dissipation was 2.3 mW (at 2.4 GHz, 1.8 V).