MuTARe: A Multi-Target, Adaptive Reconfigurable Architecture

M. Brandalero, A. C. S. Beck
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Abstract

With recent changes in transistor scaling trends, the design of all types of processing systems has become increasingly constrained by power consumption. At the same time, driven by the needs of fast response times, many applications are migrating from the cloud to the edge, pushing for the challenge of increasing the performance of these already power-constrained devices. The key to addressing this problem is to design application-specific processors that perfectly match the application's requirements and avoid unnecessary energy consumption. However, such dedicated platforms require significant design time and are thus unable to match the pace of fast-evolving applications that are deployed in the Internet-of-Things (IoT) every day. Motivated by the need for high energy efficiency and high flexibility in hardware platforms, this thesis paves the way to a new class of low-power adaptive processors that can achieve these goals by automatically modifying their structure at run time to match different applications' resource requirements. The proposed Multi-Target Adaptive Reconfigurable Architecture (MuTARe) is based upon a Coarse-Grained Reconfigurable Architecture (CGRA) that can transparently accelerate already-deployed applications, but incorporates novel compute paradigms such as Approximate Computing (AxC) and Near-Threshold Voltage Computing (NTC) to improve its efficiency. Compared to a traditional system of heterogeneous processing cores (similar to ARM's big.LITTLE), the base MuTARe architecture can (without any change to the existing software) improve the execution time by up to $1.3\times$, adapt to the same task deadline with $1.6\times$ smaller energy consumption or adapt to the same low energy budget with $2.3\times$ better performance. When extended for AxC, MuTARe's power savings can be further improved by up to $50\%$ in error-tolerant applications, and when extended for NTC, MuTARe can save further $30\%$ energy in memory-intensive workloads.
MuTARe:一个多目标、自适应、可重构的体系结构
随着晶体管缩放趋势的变化,所有类型的处理系统的设计越来越受到功耗的限制。与此同时,受快速响应时间需求的驱动,许多应用程序正在从云迁移到边缘,这对提高这些已经受到功率限制的设备的性能提出了挑战。解决这个问题的关键是设计特定于应用程序的处理器,使其完全符合应用程序的需求,并避免不必要的能耗。然而,这种专用平台需要大量的设计时间,因此无法与每天在物联网(IoT)中部署的快速发展的应用程序的速度相匹配。受硬件平台对高能效和高灵活性需求的驱动,本论文为新型低功耗自适应处理器铺平了道路,该处理器可以通过在运行时自动修改其结构以匹配不同应用的资源需求来实现这些目标。提出的多目标自适应可重构架构(MuTARe)基于粗粒度可重构架构(CGRA),可以透明地加速已部署的应用程序,但结合了新的计算范式,如近似计算(AxC)和近阈值电压计算(NTC),以提高其效率。与传统的异构处理核心系统(类似于ARM的big.LITTLE)相比,基础MuTARe架构可以(在不改变现有软件的情况下)将执行时间提高1.3倍,以1.6倍的能耗适应相同的任务截止日期,或以2.3倍的性能适应相同的低能耗预算。当扩展到AxC时,MuTARe可以在容错应用中进一步节省高达50%的能源,当扩展到NTC时,MuTARe可以在内存密集型工作负载中进一步节省30%的能源。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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